Structured State
Design state, coverage, timing, DRC/LVS status, tool logs, and physical observations should be auditable and machine-readable.
Full-Stack Deep Tech Founder · Senior Principal Architect
Building AI-native silicon systems for EDA automation and Physical AI.
I work at the intersection of Applied AI, ASIC/SoC verification, EDA orchestration, RTL-to-GDSII convergence, deterministic Physical AI, and state-fusion feedback-control architectures.
State-Fusion Intelligence
Structured evidence → AI reasoning → tool-aware action → measurable convergence.
16+ yrs
ASIC/SoC DV foundation
3
Core platform directions
Full Stack
Architecture · AI · EDA · Silicon · Product
About
Architecting the bridge between AI agents, silicon telemetry, and physical-world state.
I am a full-stack deep-tech founder and senior-principal-level architect focused on AI-native silicon systems, AI-EDA automation, deterministic Physical AI, and state-fusion feedback-control architectures.
My background includes more than 16 years of ASIC/SoC design verification experience across protocol-heavy systems, mixed-signal verification, verification planning, functional coverage, regression automation, and tapeout-oriented engineering flows.
My current work expands this foundation into Applied AI and AI-native engineering systems: AI-assisted verification, EDA orchestration, RTL-to-GDSII convergence, signoff telemetry, and deterministic Physical AI platforms.
Technical Philosophy
Automation is not enough. The goal is controlled convergence.
Evidence-Aware AI
AI agents should reason over constraints, evidence, telemetry, goals, and human review points — not isolated prompts.
Feedback Loops
Engineering systems should move from current state to target state through measurable, adjustable control loops.
Platforms
Axonmind Systems product directions
Axonmind Systems
Deterministic State-Fusion Intelligence for Physical AI and Silicon Systems.
Axonmind Systems is a deep-tech platform concept focused on AI-native engineering, silicon automation, deterministic Physical AI, and state-fusion systems.
AxonTera
Deterministic Physical AI and silicon architecture.
AxonTera explores specialized silicon and structured-state intelligence for robotics, sensor fusion, world-model acceleration, 3D + time processing, edge intelligence, low-power inference, and state-aware control.
AxonEDA
AI-native EDA automation.
AxonEDA focuses on AI-assisted design verification, UVM/cocotb generation, protocol-aware verification, regression triage, coverage closure, and multi-agent EDA workflows.
AxonSilicon
AI-assisted RTL-to-GDSII and signoff convergence.
AxonSilicon extends the vision toward implementation, timing closure, physical verification, signoff telemetry, DRC/LVS-aware state tracking, and state-fusion feedback-control loops.
Interactive Concept
State → Goal → Action → Evidence
This simple website demo shows the core idea: structured state is converted into a target, a tool-aware action is selected, and the result is captured as evidence for the next loop.
01
Input State
Coverage, timing, DRC, resource, protocol, or physical-world telemetry.
02
Target Goal
Coverage closure, timing margin, clean DRC, lower power, safer control.
03
Action Translation
Generate a constrained, auditable command for EDA tools, testbenches, or control systems.
04
Evidence Update
Capture results and feed the next loop with verifiable state.
Experience
Founder-level architecture with deep semiconductor verification roots.
Founder / Chief Architect — Full-Stack Deep Tech
Axonmind Systems · San Francisco Bay Area
Lead architecture and applied R&D for AI-native silicon systems, deterministic Physical AI, EDA automation, and state-fusion feedback-control platforms.
Senior Principal Architect / AI-EDA & Silicon Systems
Independent R&D / Consulting · San Francisco Bay Area
Develop AI-agent workflows for verification planning, testbench generation, protocol debugging, regression analysis, coverage closure, EDA orchestration, and IP-safe pilot architecture.
Senior ASIC Design Verification Engineer / Verification Architect
Previous Semiconductor and Technology Roles
Led and contributed to ASIC/SoC verification projects across PCIe, NVMe, USB, bridges, packet switches, mixed-signal blocks, and protocol-heavy systems.
Technical Stack
Cross-layer skills for deep-tech productization.
Architecture
Silicon systems, AI-native EDA, Physical AI, state-fusion feedback control, IP-safe pilots.
ASIC / SoC Verification
SystemVerilog, UVM, Verilog, Verilator, cocotb, coverage, assertions, regressions.
Protocols
PCIe, CXL, NVMe, USB, AXI, RISC-V SoC concepts, bridges, packet switches.
EDA / Silicon Flows
OpenROAD, OpenSTA, Yosys, RTL-to-GDSII, timing closure, DRC/LVS-aware workflows.
Applied AI
LLM applications, AI agents, Python tooling, PyTorch, Hugging Face, FastAPI, Gradio/Streamlit.
Productization
Prototype repositories, public-safe demos, advisor packages, first-customer discovery, pilot design.
Contact
Open to advisors, first customers, pilot partners, investors, and technical collaborators.
Relevant discussions include AI-native EDA automation, ASIC verification acceleration, RTL-to-GDSII convergence, Physical AI, deterministic state-fusion systems, silicon architecture, and IP-safe pilot programs.